Pitt Circuits and Systems Laboratory

2013

  • Y. Zhao, J. Li, and K. Mohanram, "Multi-port FinFET SRAM design,'' Proc. Great Lakes Symposium on VLSI, pp. 293--298, 2013.
  • K. Mohanram and S. Iyer, "Memsecure: Enabling orders of magnitude reduction in embedded memory certification and trust effort,'' Proc. Government Microcircuit Applications and Critical Technology Conference, 2013.
  • K. Mohanram, M. Wartell, and S. Iyer, "Mempack: An order of magnitude reduction in the cost, risk, and time for memory compiler certification,'' Proc. Design, Automation and Test in Europe, pp. 1490--1493, 2013.
  • J. Li, Y. Zhao, D. Dgien, N. A. Hunter, and K. Mohanram, "Dual-port PCM architecture for network processing,'' Proc. Non-Volatile Memories Workshop, 2013.
  • M. R. Choudhury and K. Mohanram, "Low cost concurrent error masking using approximate logic circuits,'' (accepted Jan. 2013, to appear) IEEE Trans. Computer-aided Design.
  • 2012

  • X. Yang, G. Liu, M. Rostami, A. A. Balandin, and K. Mohanram, "Graphene circuits for analog, mixed-signal, and RF electronics,'' Proc. Intl. Symposium Nanoscale Architectures, pp. 1--6, 2012.
  • K. Du, P. Varman, and K. Mohanram, "High performance reliable variable latency carry select addition,'' Proc. Design, Automation and Test in Europe, pp. 1257--1262, 2012.
  • K. Du, P. Varman, and K. Mohanram, "Static window addition: A new paradigm for the design of variable latency adders,'' Proc. Intl. Conference Computer Design, pp. 455--456, 2011.
  • M. R. Choudhury, V. Chandra, R. Aitken, and K. Mohanram, "Time-borrowing circuit designs and hardware prototyping for timing error resilience,'' (accepted Jul. 2012, to appear) IEEE Trans. Computers.
  • 2011

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    2004

    1998 to 2003

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