Towards Low Power System-on-Chip

Faculty

Jun Yang

PhD Students

Ping Zhou, Bo Zhao

Description

A system-on-chip (SoC) may contain combinations of cores of different functions such as microprocessors, memory arrays, audio and video controllers, modem, 2D and 3D graphics controllers, DSP functions etc. The high integration of vastly different function cores on-chip with the continuous technology shrinking brings forth the challenges in low power SoC designs. SoCs are widely used in consumer electronics, mobile internet devices, and embedded markets. Most of them are battery powered. An energy-efficient design can not only extends the battery life, but also allow for higher performance and higher integration of more IP blocks on-chip.

The power consumption of a chip can be expressed as: P=ACfV^2+Pleakage where A is the switching activity of functional units, C is load capacitance, f and V are clock frequency and supply voltage, and Pleakage is the leakage power of the chip. As we can see, reducing any one of the parameters, or combination of them will be effective to reducing the total power of the chip. In this project, we put forward a suite of techniques to tackle parameters A, V(f) and Pleagage simultaneously. To lower the switching activity A, we use a value encoding technique for the interconnect network of an SoC. The switching activity of the network can be significantly reduced by encoding frequent values transmitted among different blocks. To lower Pleakage, we investigate new memory technologies phase change memory (PRAM) and spin torque transfer memory (STT-RAM) in place of the current DRAM or SRAM technology. Both PRAM and STT-RAM are non-volatile, and have zero leakage in memory cells. We develop techniques to overcome their current limitations to make them practical for SoCs. To lower the voltage V and frequency f, we propose to divide the chip into separate voltage domains and apply distributed DVFS algorithms for each domain to capture opportunities to lower its own power. This will be more effective than conventional global DVFS that is applied to the whole chip.

Publications