Refereed Journal Publications

1.S. Longofono, D. Kline, R. Melhem, A. K. Jones. A CASTLE with TOWERs for Reliable, Secure PCM, IEEE Transactions on Computers – submitted.

2.J. Zhang, D. Kline, L. Fang, R. Melhem, and A. K. Jones. RETROFIT: Fault-aware Wear Leveling IEEE Computer Architecture Letters, May 2018, DOI: 10.1109/LCA.2018.2840137.

3.D. Kline, R. Melhem, A. K. Jones. Counter Advance for Reliable Encryption in Phase Change Memory IEEE Computer Architecture Letters, 2018, DOI: 10.1109/LCA.2018.2861012.

4.J. Zhang, D. Kline, L. Fang, R. Melhem, and A. K. Jones. Yielding Optimized Dependability Assurance through Bit Inversion, Integration–The VLSI Journal, August 2018 DOI: 10.1016/j.vlsi.2018.09.002.

5.J. Zhang, D. Kline, L. Fang, R. Melhem, A. K. Jones, Data Block Partitioning Methods to Mitigate Stuck-at Faults in Limited Endurance Memories, IEEE Transactions on Very Large Scale Integration (TVLSI), June 2018, DOI: 10.1109/TVLSI.2018.2858186

6.D. Kline, H. Xu, R. Melhem, A. K. Jones, Racetrack Queues for Extremely Low-Energy FIFOs, IEEE Transactions on Very Large Scale Integration (TVLSI), April 2018, DOI: 10.1109/TVLSI.2018.2819945.

7.D. Kline, N. Parshook, X. Ge, E. Brunvand, R. Melhem, P. Chrysanthis, A. K. Jones, GreenChip: A Tool for Evaluating Holistic Sustainability of Modern Computing Systems, Elsevier Journal of Sustainable Computing, Vol. 22(2019), June 2019,

DOI=10.1016/j.suscom.2017.10.001 (https://doi.org/10.1016/j.suscom.2017.10.001).

8.S. M. Seyedzadeh, A. K. Jones, R. Melhem, Counter-Based Tree Structure for Row Hammering Mitigation in DRAM, IEEE Computer Architecture Letters, Volume: 16, Issue: 1, Jan.-June 1 2017, DOI=10.1109/LCA.2016.2614497.

9.H. Xu, Y. Alkabani, R. Melhem, and A. K. Jones, FusedCache: A Naturally Inclusive, Racetrack Memory, Dual-Level Private Cache, IEEE Transactions on Multi-Scale Computing Systems, Volume: 2, Issue: 2, April-June 1 2016, DOI=10.1109/TMSCS.2016.2536020

10.M. Moeng, A. K. Jones, R. Melhem, Weighted-Tuple: Fast and Accurate Synchronization for Parallel Architecture Simulators, IEEE Transactions on Parallel and Distributed Computing and Systems, 2015, DOI=10.1109/TPDS.2015.2494589.

11.M. Seyedzadeh, R. Maddah, A. K. Jones, and R. Melhem, Improving Bit Flip Reduction for Biased and Random Data, IEEE Transactions on Computers, 2016,

DOI=10.1109/TC.2016.2525982

12.R. Khanna, V. Vahdat, K. Gassei, C. Ishwad, J. Erickson, A. K. Jones, W. E. Stanchina, and A. Vats, Low-cost, portable, isothermal nucleic acid detection with handheld, mobile device connectivity, PLOS ONE, in revision.

13.B. R. Childers, A. K. Jones, and D. Mossé, A Roadmap and Plan of Action for for Community-Supported Empirical Evaluation in Computer Architecture, ACM SIGOPS Operating Systems Review, Vol. 49, No. 1, January 2015, pp. 108-117, DOI=10.1145/2723872.2723886

14.M. Moeng, H. Xu, R. Melhem, A. K. Jones, ContextPreRF: Enhancing The Performance and Energy of GPUs with Non-Uniform Register Access (NURA), IEEE Transactions of Very Large Scale Integration (TVLSI) Briefs, Vol. 24, No. 1, January 2016, pp. 343-347,

DOI=10.1109/TVLSI.2015.2397876.

15.E. Sejdic, A. Millecamps, J. Teoli, M. A. Rothfus, N. G. Franconi, A. K. Jones, J. S. Brach, and M. H. Mickle, Assessing interactions among multiple physiological systems during walking outside a laboratory: An Android based gait monitor, Computer Methods and Programs in Biomedicine, Volume 122, Issue 3, December 2015, Pages 450-461, ISSN 0169-2607,

DOI=10.1016/j.cmpb.2015.08.012.

16.H. Xu, W. O. Collinge, L. A. Schaefer, A. E. Landis, M. M. Bilec, A. K. Jones, Towards a Commodity Solution for the Internet of Things, Elsevier Journal of Computers and Electrical Engineering, Volume 52, May 2016, Pages 138–156, DOI=10.1016/j.compeleceng.2016.03.009.

17.Y. Li, R. Melhem, A. K. Jones, A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors, IEEE Transactions on Computers, Vol. 63, No. 12, December 2014 pp. 2905–2918, DOI=10.1109/TC.2013.161,

18.Y. Li, Y. Zhang, H. Li, Y. Chen, A. K. Jones, C1C: A Configurable, Compiler-guided STT-RAM L1 Cache, ACM Transactions on Architecture and Code Optimization (TACO), Vo. 10, No. 4, December 2013, Article No. 52, pp. 52:1-52:22, DOI=10.1145/2541228.2555308 http://dx.doi.org/10.1145/2541228.2555308. (Citations: 14)

19.A. Abousamra, A. K. Jones, and R. Melhem, Ordering Circuit Establishment in Multiplane NoCs, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, October 2013, Article No. 49, pp. 49:1-49:33, DOI=10.1145/2500752 http://doi.acm.org/10.1145/2500752

20.Y. Li, Y. Zhang, Z. Sun, H. Li, Y. Chen, and A. K. Jones, Read Performance: The Newest Barrier in Scaled STT-RAM, IEEE Transactions on Very Large Scale Integration Briefs, Vol. 23, No. 6, pp. 1170-1174, June 2015. DOI=10.1109/TVLSI.2014.2326797. (Citations: 24)

21.Y. Anil, J. Stander, A. K. Jones, G. Mehta, A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric, International Journal of VLSI Design Communication Systems. Vol 4, 2013, pp. 73-91.

DOI: 10.5121/vlsic.2013.4107.

22.G. Mehta, A. K. Jones, Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing, Design Automation of Embedded Systems, 2013 vol. 17, pp. 27–51 DOI: 10.1007/s10617-013-9118-1

23.C. Saunders, A. E. Landis, L. P. Mecca, A. K. Jones, L. A. Schaefer, and M. M. Bilec, Analyzing the Practice of Life Cycle Assessment: Focus on the Building Sector, Journal of Industrial Ecology, available online, May, 2013, DOI: 10.1111/jiec.12028.

24.Y. Li, R. Melhem, and A. K. Jones, PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation for Future CMPs, ACM Transactions on Architecture and Code Optimization (TACO), Vol. 9, Issue 4, January 2013, DOI 10.1145/2400682.2400687.

25.Y. Li, Y. Zhang, Y. Chen, and A. K. Jones, Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration, IEEE Embedded Systems Letters, Vol. 4, No. 4, Dec. 2012.

26.C. L. Thiel, N. Campion, A. E. Landis, A. K. Jones, L. A. Schaefer, M. Bilec, A Materials Life Cycle Assessment of a Net-Zero Energy Building, Energies, Vol. 6, No. 2, pp 1125-1141, Feb. 2013, DOI: 10.3390/en6021125. (Citations: 33)

27.W. O. Collinge, A. E. Landis, A. K. Jones, L. A. Schaefer, M. M. Bilec. Indoor environmental quality in a dynamic life cycle assessment framework for whole buildings: Focus on human health chemical impacts. Buildings and the Environment, 62, Apr. 2013, pp. 182-190. DOI=10.1016/j.buildenv.2013.01.015 http://dx.doi.org/10.1016/j.buildenv.2013.01.015. (Citations: 23)

28.W. O. Collinge, A. E. Landis, A. K. Jones, L. A. Schaefer, M. M. Bilec. A Dynamic Life Cycle Assessment: Framework and Application to an Institutional Building. International Journal of Life Cycle Assessment, Vol. 18 No. 3, Mar. 2013, pp. 538-552. DOI=10.1007/s11367-012-0528-2 http://dx.doi.org/10.1007/s11367-012-0528-2 (Citations: 52)

29.Y. Li, R. Melhem, A. K. Jones, Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors IEEE Computer Architecture Letters, Vol. 11, No. 1, July-Dec. 2012, DOI:10.1109/L-CA.2011.35.

30.Y. Li, A. Abousamra, R. Melhem, A. K. Jones, Compiler-assisted Data Distribution and Network Configuration for Chip Multiprocessors IEEE Transactions of Parallel and Distributed Computing, Vol. 23, No. 11, November 2012, pp. 2058-2066. DOI: 10.1109/TPDS.2011.279

31.A. Abousamra, A. K. Jones, R. Melhem, Co-Design of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors, IEEE Transactions of Parallel and Distributed Computing, Volume 23, Number 6, June 2012, pp. 1038-1046. DOI: 10.1109/TPDS.2011.238. (Citations: 15)

32.A. K. Jones, D. J. Kerbyson, R. Rajamony, and C. Weems, Guest Editor’s Note: Large-Scale Parallel Processing, Parallel Processing Letters, Vol. 19, No. 4, 2009, pp. 487-490.

33.Y. Zhang and A. K. Jones, Non-Uniform “Fat-Meshes” For Chip Multiprocessors, Parallel Processing Letters, Vol. 19, No. 4, 2009, pp. 595-617.

34.A. K. Jones, D. J. Kerbyson, R. Rajamony, and C. Weems, Guest Editor’s Note: Large-Scale Parallel Processing, Parallel Processing Letters, Vol. 18, No. 4, 2008, pp. 449-451.

35.A. K. Jones, S. Shao, Y. Zhang, and R. Melhem, Symbolic Expression Analysis for Compiled Communication, Parallel Processing Letters, Vol. 18, No. 4, 2008, pp. 567-587.

36.R. Hoare, Z. Ding, and A. K. Jones, A Two-stage Hardware Scheduler for Large Cardinality Crossbar Switches, Journal of Parallel and Distributed Computing (JPDC), Vol. 68, No. 11, 2008, pp. 1437-1451.

37.G. Mehta, J. Stander, M. Baz, B. Hunsaker, and A. K. Jones Interconnect Customization for a Hardware Fabric, ACM Transactions on Design Automation for Electronic Systems (TODAES) - Vol. 14, No. 1, 2009, pp. 1-32, Article 11, DOI 10.1145/1455229.11455240. (Citations: 14)

38.S. Dontharaju, S. Tung, J. T. Cain, L. Mats, M. H. Mickle, and A. K. Jones, A Design Automation and Power Estimation Flow for RFID Systems, ACM Transactions on Design Automation for Electronic Systems (TODAES) - Vol. 14, No. 1, 2009, pp. 1-31, Article 7, DOI 10.1145/1455229.1455236. (Citations: 11)

39.S. Shao, A. K. Jones, and R. Melhem, Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems, IEEE Transactions for Parallel and Distributed Systems (TPDS), Vol. 20, No. 3, pp. 331-345. (Citations: 13)

40.A. K. Jones, R. A. Walker, Introduction to the Special Issue on Demonstrable Software Systems and Hardware Platforms II, ACM Transactions on Design Automation for Electronics Systems (TODAES), Vol. 13, No. 3, Article 38, July, 2008, DOI 10.1145/1367045.1367047.

41.A. K. Jones, S. Dontharaju, S. Tung, L. Mats, P. Hawrylak, R. R. Hoare, J. T. Cain, and M. H. Mickle, Radio Frequency Identification Prototyping, ACM Transactions on Design Automation for Electronic Systems (TODAES), Vol. 13, No. 2, April, 2008, pp. 1-21, Article 29, DOI 10.1145/1344418.1344425. (Citations: 11)

42.M. H. Mickle, J. T. Cain, A. K. Jones, Intellectual Property and Ubiquitous RFID, Recent Patents on Electrical Engineering, Vol. 1, No. 1, January 2008, pp. 59-67.

43.A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag, Journal of Microprocessors and Microsystems, Vol. 31, No. 2, March 2007, pp. 116-134. (Citations: 43)

44.S. Dontharaju, S. Tung, A. K. Jones, L. Mats, J. Panuski, J. T. Cain, and M. H. Mickle, The Unwinding of a Protocol, IEEE Applications and Practice - April, 2007, Vol. 1, No. 1, pp. 4-9.

45.A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power, IEEE Transactions on Circuits and Systems II, Vol. 53, No. 11, November 2006, pp. 1250-1254. (Citations: 14)

46.A. K. Jones, S. Dontharaju, S. Tung, P. Hawrylak, L. Mats, R. Hoare, J. T. Cain, M. H. Mickle, Passive Active Radio Frequency Identification Tags (PART), International Journal of Radio Frequency Identification Technology and Applications (IJRFITA) - Vol. 1, No. 1, 2006, pp. 52-73. (Citations: 21)

47.J. M. Lucas, R. Hoare, I. S. Kourtev, A. K. Jones, Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM), Journal of Microprocessors and Microsystems - Vol. 30, No. 7, November, 2006, pp. 445-456.

48.A. K. Jones, R. Hoare, D. Kusic, G. Mehta, J. Fazekas, and J. Foster, Reducing Power while Increasing Performance with SuperCISC, ACM Transactions on Embedded Computing Systems (TECS) - Vol. 5, No.3, August 2006, pp. 658-686. (Citations: 30)

49.J. Schuster, K. Gupta, R. Hoare, and A. K. Jones, Speech Silicon: An FPGA Architecture for Real-time, Hidden Markov Model Based Speech Recognition, EURASIP Journal on Embedded Systems (JES), Vol. 2006, Article ID 48085, 2006, Pages 1-19. (Citations: 26)

50.G. Mehta, R. R. Hoare, J. Stander, J. Lucas, B. Hunsaker, and A. K. Jones, A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture, Journal of Low Power Electronics (JOLPE) - Vol. 2, No. 2, August 2006, pp. 148-164. (Citations: 17)

51.P. J. Hawrylak, L. Mats, J. T. Cain, A. K. Jones, S. Tung, M. H. Mickle, Ultra Low-power Computing Systems for Wireless Devices, International Review on Computers and Software (IRECOS), Vol. 1, No. 1, July 2006, pp. 1-10.

52.R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, M. McCloud, Rapid VLIW Processor Customization For Signal Processing Applications Using Combinational Hardware Functions, EURASIP Journal on Applied Signal Processing (JASP), Vol. 2006, Article ID 46473, 2006, pp. 1-23. (Citations: 38)

53.A. K. Jones, J. Zhang, A. Amer, Entropy Based Evaluation of Communication Predictability in Parallel Applications, IEICE Transactions on Information & Systems, Vol. E89-D, No. 2, February 2006, pp. 469-478.

54.X. Tang, T. Jiang, A. Jones, and P. Banerjee, Behavioral Synthesis with power Estimation and Optimization for Unscheduled Data-Dominated Circuits, Journal of Low Power Electronics, Vol. 1, No.3, December 2005, pp. 259-272. (Citations: 12)

55.R. Hoare, Z. Ding, S. Tung, Rami Melhem, and A. K. Jones, A Framework for the Design, Synthesis and Cycle-Accurate Simulation of Multiprocessor Networks, Journal of Parallel and Distributed Computing, Vol. 65, No. 10, October 2005, pp. 1237-1252.

Books

1. C. Ihrig and A. K. Jones, Improving Performance and Reducing Power with Hardware Acceler- ation: Static Timing Analysis Based transformation of Combinational Logic in an High Level ASIC Synthesis Flow, VDM Publishing - in press.

Chapters in Edited Books

1.M. Bedewy, M. Abdelhakim, and A. K. Jones, Cybermanufacturing - recent technologies, promising paradigms and future challenges, Chapter 6 in “Advances in manufacturing and processing of materials and structures,” Y. Bar-Cohen, editor, CRC Press/Taylor & Francis Group, LLC., to appear

2.C. Ihrig, M. Baz, J. Stander, R. R. Hoare, B. A. Norman, O. Prokopyev, B. Hunsaker, and A. K. Jones, Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric, Chapter 11 in “Advances in Greedy Algorithms”, V. Kordic, editor, I-Tech Education and Publishing, Vienna, Austria, October 2008, pp. 193-222.

3.S. Dontharaju, S. Tung, R. R. Hoare, M. H. Mickle, J. T. Cain, A. K. Jones Design Automation for RFID Tags and Systems, Chapter 3 in “RFID Handbook: Applications, Technology, Security, and Privacy,” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008, pp. 35-64.

4.S. Tung, S. Dontharaju, L. Mats, P. J. Hawrylak, M. H. Mickle, J. T. Cain, A. K. Jones, Layers of Security for Active RFID Tags, Chapter 33 in “RFID Handbook: Applications, Technology, Security, and Privacy.” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008, pp. 603-630.

5.A. K. Jones, S. Tung, S. Dontharaju, G. J. Dhanabalan, P. J. Hawrylak, L. Mats, M. H. Mickle, and J. T. Cain, Minimum Energy/Power Considerations, Chapter 11 in “RFID Handbook: Applications, Technology, Security, and Privacy.” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008, pp. 199-230.

6.A. Jones, D. Bagchi, S. Pal, P. Banerjee, A. Choudhary. A Compiler with Power and Performance Optimizations, appears in “Power Aware Computing,” R. Graybill, R. Melhem, editors, Kluwer Academic Publishers, 2002. (Citations: 17)

Refereed Conference Proceedings (full papers)

1.D. Kline, R. Melhem, A. K. Jones. FLOWER and FaME: A Low Overhead Bit-level Fault-map and Fault-tolerance Approach for Deeply Scaled Memories, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2020.

2.S. Longofono, D. Kline, R. Melhem, A. K. Jones, Toward Secure, Reliable, and Energy Efficient Phase-change Main Memory with MACE, IGSC, 2019.

3.D. Kline, S. Longofono, S. Ollivier, E. Higgins, R. Melhem, and A. K. Jones, PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability, MASCOTS, 2019.

4.D. Kline, S. Longofono, R. Melhem, and A. K. Jones, Predicting Single Event Effects in DRAM, DFT, 2019.

5.S. Ollivier, D. Kline, R. Kawsher, R. Melhem, S. Banja, A. K. Jones. Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories, DSN 2019.

6.M. Seyedzadeh, A. K. Jones, R. Melhem. Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory, IEEE International Green and Sustainable Computing Conference (IGSC), October 2018 – Best Paper Nominee.

7.E. Brunvand, D. Kline, A. K. Jones. Dark Silicon Considered Harmful, IEEE International Green and Sustainable Computing Conference (IGSC), October 2018 – Best Paper Award.

8.M. Seyedzadeh, A. K. Jones, and R. Melhem, Mitigating Wordline Crosstalk using Adaptive Trees of Counters, ISCA, 2018.

9.M. Seyedzadeh, A. K. Jones, and R. Melhem, Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM, HPCA, 2018.

10.J. Zhang, D. Kline, R. Melhem, and A. K. Jones, Yoda: Judge me by my size, do you? Dramatically Improving Error Mitigation Through Small Increases in Encoding Bits, IEEE International Conference on Computer Design (ICCD), 2017.

11.J. Zhang, D. Kline, R. Melhem, and A. K. Jones, Dynamic Partitioning to Mitigate Stuck-at Faults in Emerging Memories, IEEE/ACM International Conference of Computer-Aided Design (ICCAD), 2017.

12.D. Kline, N. Parshook, A. Johnson, J. E. Stine, W. Stanchina, E. Brunvand, A. K. Jones, Sustainable IC Design and Fabrication, IEEE International Green and Sustainable Computing Conference (IGSC), October 2017.

13.D. Kline, R. Melhem, A. K. Jones, Holistic Energy Efficient Crosstalk Mitigation in DRAM, IEEE International Green and Sustainable Computing Conference (IGSC), October 2017.

14.D. Kline, R. Melhem, A. K. Jones, Sustainable Fault Management and Error Correction for Next-Generation Main Memories, IEEE International Green and Sustainable Computing Conference (IGSC), October 2017.

15.S. M. Seyedzadeh, D. Kline, A. K. Jones, R. Melhem, Mitigating Bitline Crosstalk Noise in DRAM Memories, MEMSYS, 2017.

16.D. Kline, N. Parshook, E. Brunvand, R. Melhem, P. K. Chrysanthis, A. K. Jones, Holistically Evaluating the Environmental Impacts in Modern Computing Systems, IEEE International Green and Sustainable Computing and Systems (IGSC), 2016.

17.I. Bayram, E. Eken, D. Kline, N. Parshook, Y. Chen, and A. K. Jones, Modeling STT-RAM Fabrication Cost and Impacts in NVSim, IEEE International Green and Sustainable Computing and Systems (IGSC), 2016.

18.Y. Alkabani, Z. Koopmans, H. Xu, A. K. Jones, and R. Melhem, Write Pulse Scaling for Energy Efficient STT-MRAM, IEEE International Symposium on VLSI (ISVLSI), 2016.

19.S. M. Seyedzadeh, R. Maddah, A. K. Jones, R. Melhem, Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2016.

20.H. Xu, M. M. Bilec, W. O. Collinge, L. A. Schaefer, A. E. Landis, and A. K. Jones, Improving Efficiency of Wireless Sensor Networks Through Lightweight In-Memory Compression, IEEE International Green and Sustainable Computing Conference (IGSC), 2015. DOI: 10.1109/IGCC.2015.7393696

21.H. Xu, M. M. Bilec, W. O. Collinge, L. A. Schaefer, A. E. Landis, and A. K. Jones, Lynx: A Self-Organizing Wireless Sensor Network with Commodity Palmtop Computers, ACM System Level Internet Prediction Workshop, 2015. DOI: 10.1109/SLIP.2015.7171712

22.D. Kline, H. Xu, F. Chen, R. Melhem, A. K. Jones, Domain-wall memory Buffer for Low-Energy NoCs, IEEE/ACM Design Automation Conference (DAC), 2015.

DOI: 10.1145/2744769.2744826

23.M. Seyedzadeh, R. Maddah, A. K. Jones, R. Melhem, PRES: A Pseudo-Random Encoding Scheme to Increase Bit Flip Reduction in Memory, IEEE/ACM Design Automation Conference (DAC), 2015. DOI: 10.1145/2744769.2755440

24.Y. Li, H. Xu, R. Melhem, A. K. Jones, Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2015. DOI: 10.1145/2742060.2742107

25.D. Kline, K. Wang, R. Melhem, A. K. Jones, MSCS: Multi-hop Segmented Circuit Switching, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2015. DOI: 10.1145/2742060.2742087

26.M. Moeng, R. Melhen, A. K. Jones, Reciprocal Abstraction for Computer Architecture Co-Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015. DOI: 10.1109/ISPASS.2015.7095812

27.H. Xu, F. Chen, R. Melhem, and A. K. Jones, Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2015. DOI: 10.1109/ASPDAC.2015.7059042

28.M. Moeng, R. Melhem, A. K. Jones, Weighted-Tuple Synchronization for Parallel Architecture Simulators, IEEE International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), September, 2014. DOI: 10.1109/TPDS.2015.2494589

29.Z. Sun, X. Bi, A. K. Jones, H. Li, Design Exploration of Racetrack Lower-level Caches, IEEE International Symposium on Low Power Electronics and Design (ISLPED), August, 2014. DOI: 10.1145/2627369.2627651

30.X. Liu, Y. Li, Y. Zhang, A. K. Jones, and Y. Chen, STD-TLB: A STT-RAM-based Dynamically-configurable Translation Lookaside Buffer for GPU Architectures, Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 355-360. DOI: 10.1109/ASPDAC.2014.6742915

31.M. Mao, G. Sun, Y. Li, A. Jones, and Y. Chen, Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 67-72 Best Paper Nominee. DOI: 10.1109/ASPDAC.2014.6742868 (Citations: 14).

32.A. K. Jones, Y. Chen, W. Collinge, H. Xu, L. Schaefer, A. Landis, and M. Bilec, Considering Fabrication in Sustainable Computing, IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 2013, pp. 206-210. DOI: 10.1109/ICCAD.2013.6691120

33.H. Xu, L. Schaefer, A. Landis, M. Bilec, and A. K. Jones, Ocelot: A Wireless Sensor Network and Computing Engine with Commodity Palmtop Computers, IEEE International Green Computing Conference (IGCC), June, 2013. DOI: 10.1109/IGCC.2013.6604482

34.A. K. Jones, L. Liao, B. Collinge, L. Schaefer, A. Landis, and M. Bilec, Green Computing: A Life-Cycle Assessment Perspective, IEEE International Green Computing Conference (IGCC) June, 2013. DOI: 10.1109/IGCC.2013.6604497

35.I. Bahar, A. K. Jones, S. Katkoori, P. H. Madden, D. Marculescu, I. L. Markov, Scaling the Impact of EDA Education: Preliminary Findings from the CCC Workshop Series on Extreme Scale Design Automation, IEEE Microelectronic Systems Education (MSE) Conference, June, 2013. DOI: 10.1109/MSE.2013.6566706

36.M. Mao, Hai Li, A. K. Jones and Y. Chen, Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems, ACM Great Lakes Symposium on VLSI (GLSVLSI) May, 2013. Best paper award. DOI: 10.1145/2483028.2483060 (Citations: 18).

37.A. Abousamra, A. K. Jones, and R. Melhem, Proactive Circuit Allocation in Multiplane NoCs,

IEEE/ACM Design Automation Conference (DAC), June, 2013. Best paper nominee DOI: 10.1145/2463209.2488778 (Citations: 11).

38.W. O. Collinge, J. Deblois, M. Sweriduk, A. E. Landis, A. K. Jones, L. A. Schaefer, M. M. Bilec, Measuring Whole-Building Performance with Dynamic Life-Cycle Assessment: A Case Study of a Green University Building., Proceedings from International Symposium on LCA and Construction, pp. 309–317 (+4 pages of appendixes), June 10-12, 2012, Nantes, France.

Print ISBN: 978-2-35158-127-8.

39.W. O. Collinge, A. E. Landis, A. K. Jones, L. A. Schaefer, M. M. Bilec, Integrating Indoor Environmental Quality Metrics in a Dynamic Life Cycle Assessment Framework For Buildings. IEEE International Symposium on Sustainable Systems and Technology (ISSST). May 16-18, 2012, Boston, Massachusetts. DOI: 10.1109/ISSST.2012.6227992

40.Y. Li and A. K. Jones, Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics, IEEE International Symposium on VLSI (ISVLSI), August, 2012. DOI: 10.1109/ISVLSI.2012.65

41.A. Abousamra, R. Melhem, A. K. Jones. Déjà Vu Switching for Multiplane NoCs, IEEE international symposium on Networks-on-Chip (NOCS), May 2012 pp. 11-18. DOI: 10.1109/NOCS.2012.9 (Citations: 25)

42.C. Saunders, A. Landis, A. K. Jones, L. Schaefer, M. Bilec, Utilizing Measured Energy Usage to Analyze Design Phase Energy Models. 2012 IEEE International Symposium on Sustainable Systems and Technology (ISSST). May 16-18, 2012, Boston, Massachusetts. DOI: 10.1109/ISSST.2012.6227982

43.Y. Li, R. Melhem, and A. K. Jones, Practically Private: Enabling High Performance CMPs Through Compiler-assisted Data Classification, ACM/IEEE Parallel Architecture and Compilation Techniques (PACT) Conference, September, 2012, pp. 231-240. DOI: 10.1145/2370816.2370852 (Citations: 23)

44.Y. Li, Y. Chen, A. K. Jones, A Software Approach for Combating Asymmetries of Non-Volatile Memories, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2012, pp. 191-196. DOI: 10.1145/2333660.2333708 (Citations: 31)

45.Y. Zhang, X. Wang, Y. Li, A. K. Jones, and Y. Chen, Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs, IEEE/ACM Design, Automation Test in Europe Conference Exhibition (DATE), March 2012, pp. 1313-1318. DOI:10.1109/DATE.2012.6176695 (Citations: 39)

46.W. O. Collinge, L. Liao, H. Xu, C. L. Saunders, M. M. Bilec, A. E. Landis, A. K. Jones, and L. A. Schaefer, Enabling Dynamic Life Cycle Assessment of Buildings with Wireless Sensor Networks, IEEE International Symposium on Sustainable Systems and Technology (ISSST), May, 2011, pp. 1-6. DOI: 10.1109/ISSST.2011.5936846 (Citations: 15)

47.Y. Li, Y. Chen, A. K. Jones, Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching, ACM Workshop on Emerging Supercomputing Technologies, 2011.

48.A. K. Jones and S. P. Levitan, Industrially inspired just-in-time (JIT) teaching, IEEE Microelectronic Systems Education (MSE) Conference, 2011. DOI: 10.1109/MSE.2011.5937079

49.H. Xu, I. Umez-Eronini, Z.-H. Mao, A. K. Jones, Towards Improving Renewable Resource Utilization with Plug-in Electric Vehicles, IEEE Innovative Smart Grid Technologies Conference, Jan. 2011. DOI: 10.1109/ISGT.2011.5759189

50.A. Abousamra, A. K. Jones, R. Melhem, Two-hop free-space based optical interconnects for Chip Multiprocessors, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), May 2011, pp. 89-96. DOI: 10.1145/1999946.1999961 (Citations: 11)

51.A. Abousamra, A. K. Jones, R. Melhem, NoC-Aware Cache Design for Multithreaded Execution on Tiled Chip Multiprocessors, ACM High Performance and Embedded Architectures and Compilers (HiPEAC), Jan. 2011, pp. 197-205. DOI: 10.1145/1944862.1944891

52.Y. Li, A. Abousamra, R. Melhem, A. K. Jones, Compiler-assisted Data Distribution for Chip Multiprocessors, ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010, pp. 501-512. DOI: 10.1145/1854273.1854335 (Citations: 44)

53.C. Ihrig, R. Melhem, and A. K. Jones, Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip Multiprocessors, IEEE/ACM Design Automation Conference (DAC), p. 431-436, 2010. DOI: 10.1145/1837274.1837383

54.H. Wang, G. Reed, A. K. Jones, Analysis of Recovery Current and Core Structure of DC Power Supply in Electronic Current Transformer, IEEE International Symposium on Industrial Electronics (ISIE) 2010. DOI: 10.4028/www.scientific.net/AMR.284-286.2170

55.H. Wang, G. Reed, A. K. Jones, Review: DC Power Supply of High Voltage Active Electronic Current Transformer, IEEE International Symposium on Industrial Electronics (ISIE) 2010.

56.H. Wang, H. Xu, and A. K. Jones, Crucial Issues in Logistic Planning for Electric Vehicle Battery Application and Service, International Symposium on Traffic Information and Logistic Engineering (ISTILE), 2010. DOI: 10.1109/ICOIP.2010.125 (Citations: 12)

57.R. O’Conner, H. Bassi, B. Grainger, E. Taylor, G. Reed, A. K. Jones, and Z. Mao, Integrated Multisource Generation and Control for Increasing Renewable Generation Utilization, IEEE Annual Power Meeting, 2010.

58.Y. Li, R. Melhem, and A. K. Jones, Compiler-based Data Classification for Hybrid Caching, Proceedings of the ACM Workshop on the Interaction between Compilers and Computer Architectures (INTERACT), 2010. DOI: 10.1145/1739025.1739030

59.A. Abousamra, R. Melhem, A. K. Jones, Winning with Pinning in NoC, IEEE Hot Interconnects (HOTI), 2009. DOI: 10.1109/HOTI.2009.15 (Citations: 17)

60.C. J. Ihrig, G. J. Dhanabalan and A. K. Jones, A Low-power CMOS Thyristor Based Delay Element With Programmability Extensions, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2009, pp. 297-302. DOI: 10.1145/1531542.1531611

61.Y. Zhang and A. K. Jones, Non-Uniform Fat-Meshes for Chip Multiprocessors, IEEE Workshop of Large Scale Parallel Processing (LSPP), 2009, pp. 1-8. DOI: 10.1109/IPDPS.2009.5161093

62.S. Shao, Y. Zhang, A. K. Jones, R. Melhem, Symbolic Expression Analysis for Compiled Communication, IEEE Workshop on Large Scale Parallel Processing (LSPP), 2008, pp. 286.1 - 286.8. DOI: 10.1109/IPDPS.2008.4536344

63.S. Tung and A. K. Jones, Physical Layer Design Automation for RFID Systems, IEEE Reconfigurable Architecture Workshop (RAW), 2008, pp. 117.1 - 117.8. DOI: 10.1109/IPDPS.2008.4536530 (Citations: 14)

64.G. Mehta, C. Ihrig, and A. K. Jones, Reducing Energy by Exploring Heterogeneity in a Coarse-grain Fabric, IEEE Reconfigurable Architecture Workshop (RAW), 2008, pp. 104.1 - 104.8. DOI: 10.1109/IPDPS.2008.4536532 (Citations: 10)

65.Y. Yu, R. R. Hoare, and A. K. Jones, A CAM-based Intrusion Detection System for Single-packet Attack Detection, IEEE Reconfigurable Architecture Workshop (RAW), 2008, pp. 119.1 - 119.8. DOI: 10.1109/IPDPS.2008.4536531

66.A. K. Jones, S. R. Dontharaju, L. Mats, James T. Cain, and M. H. Mickle, Exploring RFID Prototyping in the Virtual Laboratory, IEEE Microelectronic Systems Education Conference, 2007, pp. 137-138. DOI: 10.1109/MSE.2007.41

67.A. K. Jones, S. Levitan, R. A. Rutenbar, and Y. Xie, Collaborative VLSI-CAD Instruction in the Digital Sandbox, IEEE Microelectronic Systems Education Conference, 2007, pp. 141-142. DOI: 10.1109/MSE.2007.29

68.A. K. Jones, R. R. Hoare, J. St. Onge, J. Lucas, S. Shao, and R. Melhem, Linking Compilation and Visualization for Massively Parallel Programs, Workshop on Advances in Parallel and Distributed Computational Models (APDCM), pp. 228.1 - 228.8, 2007. DOI: 10.1109/IPDPS.2007.370470

69.C. J. Ihrig, J. Stander, and A. K. Jones, Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions, IEEE Workshop on Advances in Parallel and Distributed Computational Models (APDCM), pp. 227.1 - 227.8, 2007. DOI: 10.1109/IPDPS.2007.370468

70.G. Mehta, J. Stander, M. Baz, B. Hunsaker, A. K. Jones, Interconnect Customization for a Coarse-grained Reconfigurable Fabric, IEEE Reconfigurable Architecture Workshop (RAW), pp. 165.1 - 165.8, 2007. DOI: 10.1109/IPDPS.2007.370370 (Citations: 12)

71.Z. Ding, R. Hoare, A. K. Jones, R. Melhem, Level-wise Scheduling Algorithm for Fat Tree Interconnection Networks, IEEE/ACM Supercomputing (SC), 2006, pp. 165.1 - 165.9. DOI: 10.1109/SC.2006.40 (Citations: 23)

72.R. Hoare, Z. Ding, A. K. Jones, A Near-optimal Real-time Hardware Scheduler for Large Cardinality Crossbar Switches, IEEE/ACM Supercomputing (SC), 2006, pp. 164.1 - 164.12. DOI: 10.1109/SC.2006.3

73.A. K. Jones, R. Hoare, S. R. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, and M. H. Mickle, A Field Programmable RFID Tag and Associated Design Flow, IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), 2006, pp. 165-174. DOI: 10.1109/FCCM.2006.7 (Citations: 21)

74.S. Shao, A. K. Jones, R. Melhem, A Compiler-based Communication Analysis Approach for Multiprocessor Systems, IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2006, DOI: 10.1109/IPDPS.2006.1639322, 10 pages. (Citations: 32)

75.Y. Yu, R. Hoare, A. K. Jones, R. Sprang, A Hybrid Encoding Scheme for Efficient Single-cycle Range Matching in Content Addressable Memory, IEEE International Symposium on Circuits and Systems (ISCAS), 2006, pp. 791-794. DOI: 10.1109/ISCAS.2006.1692704

76.A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag, IEEE/ACM Design Automation Conference (DAC), 2006, pp. 131-136. DOI: 10.1145/1146909.1146948 (Citations: 43)

77.K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. J. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. A. Walker, On the Feasibility of Optical Circuit Switching for High Performance Computing Systems, IEEE/ACM Supercomputing Conference (SC), 2005. DOI: 10.1109/SC.2005.48 (Citations: 178)

78.D. Kusic, R. Hoare, A. K. Jones, J. Fazekas, J. Foster, Extracting Speedup from C-code with Poor Instruction-level Parallelism, IEEE Workshop of Massively Parallel Processing (WMPP), 2005. DOI: 10.1109/IPDPS.2005.216

79.A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, and J. Foster, An FPGA-based VLIW Processor with Custom Hardware Execution, ACM International Symposium on Field-Programmable Gate Arrays (FPGA) 2005, pp. 107-117. DOI: 10.1145/1046192.1046207 (Citations: 98)

80.Z. Ding, R. Hoare, A. K. Jones, D. Li, S. Shao, S. Tung, J. Zheng and R. Melhem, Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks, IEEE International Parallel & Distributed Processing Symposium, 2005. DOI: 10.1109/IPDPS.2005.416 (Citations: 33)

81.X. Tang, T. Jiang, A. Jones, P. Banerjee, Behavioral Synthesis of Data Dominated Circuits for Minimal Energy Implementation, IEEE International Conference on VLSI Design, Taj Bengal, Kolkata, India, January 2005, pp. 267-273. DOI: 10.1109/ICVD.2005.62 (Citations: 13)

82.J. Lucas, R. Hoare, I. Kourtev, A. Jones, LURU: Global Scope FPGA Technology Mapping with Content-Addressable Memories, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Isreal, December, 2004, pp. 599-602. DOI: 10.1109/ICECS.2004.1399752

83.A. Jones, R. Hoare, I. Kourtev, J. Fazekas, D. Kusic, J. Foster, S. Boddie, A. Muaydh, A 64-way VLIW/SIMD FPGA Processing Architecture and Design Flow. IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Israel, December, 2004, pp. 499-502. DOI: 10.1109/ICECS.2004.1399727 (Citations: 19)

84.B. Brady, A. Jones, I. Kourtev, Efficient CAD Development for Emerging Technologies using Objective-C and Cocoa, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Israel, December 2004, pp. 369-372. DOI: 10.1109/ICECS.2004.1399695

85.A. Jones, X. Tang, P. Banerjee, Compile-time Simulation for Low-Power Optimization using SystemC, IASTED Modelling and Simulation Conference, Marina Del Ray, CA, 2004, pp. 78-83.

86.T. Jiang, X. Tang, A. Jones, P. Banerjee, Optimizing Power While Exploiting Fine Grain Parallelism on FPGAs, IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2003, pp. 357-362.

87.R. Mukherjee, A. Jones, P. Banerjee, System Level Synthesis of Multiple IP Blocks in the Behavioral Synthesis Tool, IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2003, pp.363-368. Best Paper Award Nominee

88.X. Tang, T. Jiang, A. Jones, P. Banerjee, Compiler Optimizations in the PACT HDL Behavioral Synthesis Tool for ASICs and FPGAs, IEEE International SoC Conference (SoC), September 2003, pp. 189-192. (Citations: 14)

89.A. Jones, D. Bagchi, S. Pal, X. Tang, A. Choudhary, P. Banerjee, PACT HDL: A C Compiler with Power and Performance Optimizations, ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, October 2002, pp. 188-197. DOI: 10.1145/581630.581659 (Citations: 38)

90.A. Jones, A. Nayak, P. Banerjee. Parallel Implementation of Matrix and Signal Processing Libraries on FPGAs, IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS), Anaheim, CA, August 2001, pp. 370-377. Best Paper Award Nominee

91.P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Chang, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, MATCH: A MATLAB Compilation Environment for Configurable Computing Systems, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2000, pp. 39-48. DOI: 10.1109/FPGA.2000.903391 (Citations: 155)

92.S. Periyacheri, A. Jones, A. Nayak, D. Zaretsky, P. Banerjee, N. Shenoy, A. Choudhary. Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB, IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 1999), Cambridge, MA, November, 1999. (Citations: 28)

Refereed Conference Proceedings (extended abstracts)

1.J. DeBlois, W. Collinge, A. K. Jones, M. M. Bilec, L. A. Schaefer , Modeling a Multi-Purpose Public Building with Stochastic Gains and Occupancy Schedules. ASHRAE Winter Meeting, 2014, pp. 12093

2.A. K. Jones, EDA for Extreme Scale Systems: Design Abstractions, Metrics, and Benchmarks, GLSVLSI, 2014. DOI: 10.1145/2591513.2597170

3.W. O. Collinge, M. M. Bilec, A. E. Landis, A. K. Jones, and L. A. Schaefer, Scenario Modeling for Dynamic Life Cycle Assessment of Commercial and Institutional Building., Proceedings of LCA XI, October 4-6, 2011, Chicago, Illinois.

4.A. Abousamra, A. K. Jones, R. Melhem, NoC Aware Cache Design for Chip Multiprocessors, ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010. DOI: 10.1145/1854273.1854354

5.J. Lucas, R. Hoare, I. Kourtev, and A. K. Jones, Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM), Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), 2006, pp. 299-300. DOI: 10.1109/FCCM.2006.68

6.G. Mehta, R. Hoare, J. Stander, A. K. Jones, A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture, Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), pp. 309-310. DOI: 10.1109/FCCM.2006.9 (Citations: 17)

7.G. Mehta, R. Hoare, J. Stander, A. Jones, Design Space Exploration for Low-Power Reconfigurable Fabrics, Proc. of IEEE/ACM Reconfigurable Architectures Workshop (RAW), 2006. DOI: 10.1109/IPDPS.2006.1639484 (Citations: 15)

8.J. Lucas, R. Hoare, I. Kourtev, and A. K. Jones,  Optimizing technology mapping for FPGAs using CAMs, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2005, pp. 293-294. DOI: 10.1109/FCCM.2005.50

9.R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power, Proc. of HPEC, September 2005, pp. 5-6. (Citations: 14)

10.R. Mukherjee, A. Jones, P. Banerjee, Handling Data Streams while Compiling C Programs onto Hardware, International Symposium on VLSI (ISVLSI), Lafayette, Louisiana, February, 2004, pp. 271-272. DOI: 10.1109/ISVLSI.2004.1339553

11.A. Jones, P. Banerjee, An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2003, pp.284-285. DOI:10.1145/611817.611873

12.A. Jones, P. Banerjee, An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, California, February, 2003, pp. 244. DOI: 10.1145/611817.611873